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AZ12000, az12001 phase - locked loop clock generator 1630 s. stapley dr., suite 12 7 ? mesa, ar izona 85204 ? usa ? (480) 962-5881 ? fax (480) 890-2541 www.azmicrotek.com arizona microtek, inc. package availability package part no. marking notes mlp 24 (4x4) AZ12000k AZ12000 1,2 mlp 24 (4x4) az12001k az12001 1,2 die AZ12000xp n/a 3 die az12001xp n/a 3 1 add r1 at end of part number for 7 inch (1k parts), r2 for 13 inch (2.5k parts) tape & reel. 2 date code format: ?yy? for year followed by ?ww? for week. 3 waffle pack features ? pecl (AZ12000) or lvds (az12001) outputs ? operating range 3.0v to 5.5v ? internal crystal oscillator driver ? internal edge-matching phase/frequency detector ? internal charge-pump and integrator amplifier ? internal or external vco ? divide by 4, 8, 16, 32 ? rf bipolar design for low phase noise ? available in a 4x4mm mlp package description the AZ12000/az12001 contains all of the functional elements n ecessary to implement a phase-locked loop for clock multiplication at frequencies up to 800 mhz. a reference crystal oscillator driver operates at frequencies up to 200 mhz providing support for 4 times multiplication. the dynamic properties of the pll are under the control of the user through selection of the desired external components. block diagram phase/ freq detect charge pump vco mux divide by 4,8,16,32 outpt drvr input rcvr mux ds1 ds2 q q refin v bb refout 4ma 470 ? buffer tank extvco extvco vcosel vbb intref intsum intout cpref cpout cppol integrator v cc v ee v ee vco output vcov cc
AZ12000 az12001 january 2005 * rev - 3 www.azmicrotek.com 2 absolute maximum ratings are those values beyond which device life may be impaired. symbol characteristic rating unit v cc power supply (v ee = gnd) 0 to +6.0 vdc v i input voltage (v ee = gnd) 0 to +6.0 vdc i out ecl/pecl output current ? continuous ? surge 40 80 ma t a operating temperature range -40 to +85 c t stg storage temperature range -65 to +150 c 3 4 vcov cc tank vcosel n/c v cc q q ds2 intout intsum intref cpout refin extvco v ee 16 15 14 13 12 11 10 9 8 7 6 5 refout ds1 extvco cppol cpref v ee v cc v ee v bb 17 18 19 20 21 22 23 24 2 1 pinout: AZ12000, az12001 (24 pin mlp, top view) otto ente p e et open o tie to v
AZ12000 az12001 january 2005 * rev - 3 www.azmicrotek.com 3 AZ12000 functional pi n descriptions pin no pin name functional description logic level refin reference crystal resonator input this pin includes an on-chip 470 pull down resistor to v bb . the input from the resonator circuit should be ac coupled. refout crystal resonator output drive this pin is an inverted and amplified version of the signal on the refin pin. the gain from refin to refout is approximately 20. the ic includes a 4 ma on-chip current source. if more current is needed, the refout pin may be connected to v ee through a resistor to provide up to 8 ma additional current. ecl/pecl cpref charge pump reference output the pin voltage is nominally 1.2 volts below v cc . if an external integrator is used, cpref should be connected to the integrator reference input through a bias current cancellation network. cpout charge pump output the charge pump output voltage is v(cpref) 0.3v during a phase correction pulse. when there is no correction pulse the output goes high impedance. if an external integrator is used, cpout should be connected to the input integrator resistor. cppol charge pump polarity logic low on this pin causes cpout to go low when the vco frequency is too low, and go high when the vco frequency is too high. logic high on this pin causes cpout to go low when the vco frequency is too high, and go high when the vco frequency is too low. this pin should be low when the internal vco is used. if this pin is left open it is pulled to the high condition. cmos/ttl compatible intref integrator reference input this pin should be connected to cpref through a bias current cancellation network intsum integrator summing junction this pin is the summing junction for the integrator amplifier intout integrator output vcosel internal/external vco select logic high on this pin enables the internal vco. logic low on this pin disables the internal vco and allows use of the extvco inputs. if this pin is left open it is pulled to the high condition. cmos/ttl compatible tank vco tank the tank components connect between this pin and v cc . extvco extvco external vco input the external vco input pins should be driven differentially for best performance. ecl/pecl ds2 ds1 divide select vco divide ratios are selected as shown: ds2 ds1 ratio low low 4 low high 8 high low 16 high high 32 if the pins are left open they are pulled to the high condition. cmos/ttl compatible q q clock output these pins are the main (multiplied) clock output. ecl/pecl n/c no connect this pin is used during factory test. it mist be left open. v bb reference voltage output this pin is used to bias the refin signal. it must be bypassed externally to the vee pins with a 0.01 f capacitor. v cc positive supply +3.0 to +5.5 v for pecl mode, ground for ecl mode. vcov cc vco positive supply +3.0 to +5.5 v for pecl mode, ground for ecl mode. v ee negative supply ground for pecl mode, ?3.0 to ?5.5 v for ecl mode.
AZ12000 az12001 january 2005 * rev - 3 www.azmicrotek.com 4 az12001 functional pi n descriptions pin no pin name functional description logic level refin reference crystal resonator input this pin includes an on-chip 470 pull down resistor to v bb . the input from the resonator circuit should be ac coupled. refout crystal resonator output drive this pin is an inverted and amplified version of the signal on the refin pin. the gain from refin to refout is approximately 20. the ic includes a 4 ma on-chip current source. if more current is needed, the refout pin may be connected to v ee through a resistor to provide up to 8 ma additional current. pecl cpref charge pump reference output the pin voltage is nominally 1.2 volts below v cc . if an external integrator is used, cpref should be connected to the integrator reference input through a bias current cancellation network. cpout charge pump output the charge pump output voltage is v(cpref) 0.3v during a phase correction pulse. when there is no correction pulse the output goes high impedance. if an external integrator is used, cpout should be connected to the input integrator resistor. cppol charge pump polarity logic low on this pin causes cpout to go low when the vco frequency is too low, and go high when the vco frequency is too high. logic high on this pin causes cpout to go low when the vco frequency is too high, and go high when the vco frequency is too low. this pin should be low when the internal vco is used. if this pin is left open it is pulled to the high condition. cmos/ttl compatible intref integrator reference input this pin should be connected to cpref through a bias current cancellation network intsum integrator summing junction this pin is the summing junction for the integrator amplifier intout integrator output vcosel internal/external vco select logic high on this pin enables the internal vco. logic low on this pin disables the internal vco and allows use of the extvco inputs. if this pin is left open it is pulled to the high condition. cmos/ttl compatible tank vco tank the tank components connect between this pin and v cc . extvco extvco external vco input the external vco input pins should be driven differentially for best performance. pecl ds2 ds1 divide select vco divide ratios are selected as shown: ds2 ds1 ratio low low 4 low high 8 high low 16 high high 32 if the pins are left open they are pulled to the high condition. cmos/ttl compatible q q clock output these pins are the main (multiplied) clock output. lvds n/c no connect this pin is used during factory test. it must be left open. v bb reference voltage output this pin is used to bias the refin signal. it must be bypassed externally to the vee pins with a 0.01 f capacitor. v cc positive supply +3.0 to +5.5 v vcov cc vco positive supply +3.0 to +5.5 v v ee negative supply ground
AZ12000 az12001 january 2005 * rev - 3 www.azmicrotek.com 5 AZ12000 (pecl output) dc characteristics (v cc = +3.0 to +5.5 v, v ee = gnd) -40 c 0 c 25 c 85 c symbol characteristic min max min max min typ max min max unit v bb reference voltage v cc -1.38 v cc -1.26 v cc -1.38 v cc -1.26 v cc -1.38 v cc -1.31 v cc -1.26 v cc -1.38 v cc -1.26 v r pd refin pull-down resistor to v bb 470 i cs refout current source 4.0 ma v hctl high level integrator output v cc -1.0 v v lctl low level integrator output v ee +0.5 v v oh output high voltage 1 q q v cc -1085 v cc -880 v cc -1025 v cc -880 v cc -1025 v cc -955 v cc -880 v cc -1025 v cc -880 mv v ol output low voltage 1 q q v cc -1830 v cc -1555 v cc -1810 v cc -1620 v cc -1810 v cc -1705 v cc -1620 v cc -1810 v cc -1620 mv v ih input high voltage, pecl/ecl extvco extvco v cc -1165 v cc -880 v cc -1165 v cc -880 v cc -1165 v cc -880 v cc -1165 v cc -880 mv v il input low voltage, pecl/ecl extvco extvco v cc -1810 v cc -1475 v cc -1810 v cc -1475 v cc -1810 v cc -1475 v cc -1810 v cc -1475 mv v ih input high voltage, ttl/cmos cppol vcosel ds2 ds1 v ee +2.0 v ee +2.0 v ee +2.0 v ee +2.0 v v il input high voltage, ttl/cmos cppol vcosel ds2 ds1 v ee +0.8 v ee +0.8 v ee +0.8 v ee +0.8 v i cc (i ee ) power supply current 55 58 45 58 60 ma 1. load is 50 to v cc -2v
AZ12000 az12001 january 2005 * rev - 3 www.azmicrotek.com 6 az12001 (lvds output) dc characteristics (v cc = +3.0 to +5.5 v, v ee = gnd) -40 c 0 c 25 c 85 c symbol characteristic min max min max min typ max min max unit v bb reference voltage v cc -1.38 v cc -1.26 v cc -1.38 v cc -1.26 v cc -1.38 v cc -1.31 v cc -1.26 v cc -1.38 v cc -1.26 v r pd refin pull-down resistor to v bb 470 i cs refout current source 4.0 ma v hctl high level integrator output v cc -1.0 v v lctl low level integrator output v ee +0.5 v v oh output high voltage 1 q q mv v ol output low voltage 1 q q mv v ih input high voltage, pecl/ecl extvco extvco v cc -1165 v cc -880 v cc -1165 v cc -880 v cc -1165 v cc -880 v cc -1165 v cc -880 mv v il input low voltage, pecl/ecl extvco extvco v cc -1810 v cc -1475 v cc -1810 v cc -1475 v cc -1810 v cc -1475 v cc -1810 v cc -1475 mv v ih input high voltage, ttl/cmos cppol vcosel ds2 ds1 v ee +2.0 v ee +2.0 v ee +2.0 v ee +2.0 v v il input high voltage, ttl/cmos cppol vcosel ds2 ds1 v ee +0.8 v ee +0.8 v ee +0.8 v ee +0.8 v i cc (i ee ) power supply current 60 60 60 ma 1. 100 between outputs
AZ12000 az12001 january 2005 * rev - 3 www.azmicrotek.com 7 az 12000 (pecl output ) ac characteristics (v cc = +3.0 to +5.5 v, v ee = gnd) -40 c 25 c 85 c symbol characteristic min typ max min typ max min typ max unit a v1 gain, refin to refout 20 v/v z o output impedance, refout tbd a pd phase detector gain 20.3 radians/v f vco vco frequency (internal or external) 800 mhz t r / t f output rise & fall times (20% - 80%) q q 120 120 ps az12001 (lvds output) ac characteristics (v cc = +3.0 to +5.5 v, v ee = gnd) -40 c 25 c 85 c symbol characteristic min typ max min typ max min typ max unit a v1 gain, refin to refout 20 v/v z o output impedance, refout tbd a pd phase detector gain 20.3 radians/v f vco vco frequency (internal or external) 800 mhz t r / t f output rise & fall times (20% - 80%) q q ps
AZ12000 az12001 january 2005 * rev - 3 www.azmicrotek.com 8 internal reference oscillator the pll reference can be generated either with an internal oscillator or with an external source. in either case, the input is the refin pin. this should be ac coupled since the input is internally biased to v bb . the refout pin should be left open when an external reference is used. the exact topology of the crystal circuit will vary based on the resonant mode of the crystal. the circuit shown is for a series resonant crystal. the ac gain between the refin and refout pins is approximately 20. this value is sufficient to overcome crystal matching network losses without phase noise degradation caused by an excessive drive level. an internal current source on refout eliminates the need for an external load resistor. outpt drvr input rcvr refin v bb refout 4ma 470 vbb v ee (ground) c ground c4 f r o
AZ12000 az12001 january 2005 * rev - 3 www.azmicrotek.com 9 loop filter design the combination of the phase detector, amplifier, vco and divider form a second-order phase-locked loop. proper selection of the loop components is important to obtain stable, low jitter operation. the loop bandwidth (or natural frequency, n ) and damping factor ( ) are the two major driving forces that define the loop?s response to a disturbance. the value of is typically 0.7 to ensure the fastest step response consistent with no ringing. however in many oscillator application may be 3 or higher to provide further phase noise reduction. n is chosen as a compromise between settling time, vco jitter and reference feedthrough. these values can be computed by the following equations: 1 1 vco n k k n = 2 2 n = 1 1 1 c r = 1 2 2 c r = = k phase detector gain (20.3 radians/v) = vco k vco gain (radians/sec/volt) = n frequency divisor value (4,8, 16 or 32) the component definitions are shown in the figure below. r3 should be equal to r1 to minimize integrator offsets. charge pump intref intsum intout cpref cpout integrator r c r r vco control voltage fcpi
AZ12000 az12001 january 2005 * rev - 3 www.azmicrotek.com 10 internal vco the internal vco is designed for reliable, low jitter operation up to 800 mhz. it operates as a single terminal negative impedance type circuit. the tank circuit should have a minimum q of 12 for reliable operation. the series combination of cv and c1 resonate with l1 to set the operating frequency. the vco control voltage is isolated through an inductor or resistor and changes the varactor capacitance based on that control voltage. note that the cppol pin should be tied high for internal vco operation since the tank frequency decreases with increasing control voltage. external vco when vcosel is high, the internal vco is disabled and the extvco, extvco pair is enabled. that i nput pair is sine wave and pecl compatible. the cppol pin sets the frequency slope polarity based on the operation of the external vco. when cppol is low, the charge pump generates pulses for an integrator and loop filter assuming the vco frequency goes lower as the integrator output voltage increases. when cppol is high, pulses are generated for a vco in which the frequency goes higher as the integrator output voltage increases. vco c tank tank aat nt ta t
AZ12000 az12001 january 2005 * rev - 3 www.azmicrotek.com 11 application circuit a typical application circuit is shown in figure 4. this drawing shows use of the internal reference oscillator and internal vco. f phase/ freq detect charge pump vco mux divide by 4,8,16,32 outpt drvr input rcvr mux ds1 ds2 q q refin v bb refout 4ma 470 buffer extvco vcosel vbb intref intsum intout cpref cpout cppol integrator vcov cc , v cc v ee v ee vco output extvco r2 c1 y1 r1 r3 l1 c2 tank l2 l3 c3 pecl or lvds output vcc ground connect to vcc or ground for required division ratio c4 001 f tank cv varactor AZ12000 az12001 a
AZ12000 az12001 january 2005 * rev - 3 www.azmicrotek.com 12 package diagram mlp 24 millimeters dim min max a 0.80 1.00 a1 0.00 0.05 a3 0.25 ref b 0.18 0.30 d 3.90 4.10 d2 2.65 2.95 e 3.90 4.10 e2 2.65 2.95 e 0.50 bsc l 0.35 0.45 aaa 0.25 bbb 0.10 ccc 0.10 notes 1. dimensioning and tolerancing conform to asme t14-1994. 2. the terminal #1 and pad numbering convention shall conform to jesd 95-1 spp-012. 3. dimension b applies to metallized pad and is measured between 0.25 and 0.30mm from pad tip. 4. coplanarity applies to the exposed pad as well as the terminals.
AZ12000 az12001 january 2005 * rev - 3 www.azmicrotek.com 13 arizona microtek, inc. reserves the right to change circuitry and specifications at any time without prior notice. arizona mic rotek, inc. makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does a rizona microtek, inc. assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. arizona microtek, inc. does not convey a ny license rights nor the rights of others. arizona microtek, inc. products are not designed, intended or authorized for use as component s in systems intended to support or sustain life, or for any other application in which the failure of the arizona microtek, inc. product co uld create a situation where personal injury or death may occur. should buyer purchase or use arizona microtek, inc. products for any such unintended or unauthorized application, buyer shall indemnify and hold arizona microtek, inc. and its officers, employees, subs idiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising ou t of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim al leges that arizona microtek, inc. was negligent regarding the design or manufacture of the part.

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